1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a DRAM (Dynamic Random Access Memory) carrying out a self-refreshing operation.
2. Description of the Background Art
In the DRAM serving as a semiconductor memory device, a memory cell is self-refreshed. In one method of self-refreshing, a memory cell is refreshed in a refresh cycle generated by an internal circuit of a chip on which the DRAM is formed.
In the self-refreshing operation, a memory cell can be refreshed without an externally applied refresh cycle. More specifically, a relatively long refresh cycle is generated in an internal circuit of a chip, and the refreshing operation is carried out by the internal circuit of the chip in the generated refresh cycle.
Description will now be given of a conventional self-refreshing operation. FIG. 37 is a timing chart showing one example of timings of the conventional self-refreshing operation.
Referring to FIG. 37, after an external column address strobe signal extCAS falls to an L or logical low level, an external row address strobe signal extRAS falls to the L level. When these signals both hold the L level for a predetermined period after that timing, that is, a CAS Before RAS timing (hereinafter referred to as a "CBR timing"), a self-refresh enable signal SRE defining a self-refreshing period rises to an H or logical high level.
In response to the signal SRE attaining the H level, an internal row address strobe signal intRAS generates a relatively long refresh cycle trc within a chip. In response to the signal intRAS, the refreshing operation is carried out. Also during the self-refreshing operation, an internal power supply voltage intVcc is held constant.
A problem associated with such a self-refreshing operation is how to make a refresh cycle longer, and how to reduce current consumption both in a stand-by period and an active period in the self-refreshing operation.
However, in a 16 MDRAM and other devices developed thereafter, scale down of a power supply voltage has not caught up with progress of miniaturization. Therefore, in order to implement high integration density while securing reliability of the device, an internal voltage down-converting circuit has been provided in the chip. The internal voltage down-converting circuit generates a low internal power supply voltage obtained by down-converting an external power supply voltage.
In order to implement high speed access in a device operating based on the internal power supply voltage lower than the external power supply voltage, a word line boosted voltage generating circuit has also been provided in the chip.
As described above, the internal voltage down-converting circuit and the boosted voltage generating circuit were provided in the chip in the DRAM. Therefore, these circuits increased current consumption in a stand-by period or the like in the self-refreshing operation.
One method of reducing an active current in the self-refreshing operation is to decrease the external power supply voltage in the self-refreshing operation. In this method, however, it is necessary to control the power supply voltage out of the chip. Therefore, it was difficult to control increase and decrease of the power supply voltage on a memory board.